The present application relates generally to semiconductor devices and includes methods and structures for improving a chemical mechanical planarization (CMP) process, which may be used to prepare a region of a semiconductor device for silicide formation.
An important capability for manufacturing reliable integrated circuits is to prevent contact between two structures such that a short does not form. To achieve this isolation, trench structures, such as those used in Shallow Trench Isolation (STI), are formed. These trenches are filled with a dielectric and a CMP process is performed to flatten the surface of the semiconductor device in preparation for the formation of other structures. The CMP process stops when a surface such as a surface of a SiN layer, a mask layer or a substrate is reached however some of the dielectric material from the trenches continues to be removed. This phenomenon is an example of a dishing effect. Thus, structures that are formed over the filled in trenches will be at a lower height than those formed over the substrate, which leads to problems in subsequent processing steps.